STM8S datasheet(462/467 Pages) STMICROELECTRONICS

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Revision history

RM0016

462/467

DocID14587 Rev 14

07-May-2013

Added low density STM8AF devices.

Replaced all references of STM8A with STM8AF.

Updated Table 14: Devices with 4 trimming bits.

Updated Section 11.5: Unused I/O pins.

Updated Halt/ Active-halt description in Table 68: beCAN behavior in

low power modes.

Added UART4 in Section 22: Universal asynchronous receiver

transmitter (UART).

Updated Section 23.4.4: Time triggered communication mode.

19-Jun-2014

– Introduction: updated the description of the medium and high

density STM8AF devices.

– Section 4.4.1: STM8S and STM8AF memory organization:

updated the description of Medium density STM8AF devices.

– Section 23: Controller area network (beCAN): changed the default

reset value for CAN_MSR.

– Section 6: Interrupt controller (ITC): replaced IRS_CC with

ISR_CC in the footnote of Table 9: Interrupt enabling/disabling

inside an ISR.

– Section 11: General purpose I/O ports (GPIO): removed the

footnote (1) in Table 21: I/O port configuration summary

– Section 24: Analog/digital converter (ADC): replaced the first

sentence in Section 24.5.6: Analog watchdog, and replaced

AWDENx with AWENx in the heading of Table 74.

– Section 21: Inter-integrated circuit (I2C) interface: added the

section “SCL master clock generation”, and updated

Section 21.4.2: I2C master mode, Section 21.7.3: Frequency

(I2C_TRISER).

– Section 24.5.3: Channel selection: corrected a typo on ACD_CSR.

– Updated Section 11.7.4: Schmitt trigger.

23-Mar-2015

Updated:

– the document title and the Introduction on the cover page,

– the very first sentence in Section 17.4.6: Synchronization between

TIM1, TIM5 and TIM6 timers,

– TS[2:0] bit definitions in Section 17.7.3: Slave mode control

– TS[2:0] bit definitions in Section 18.6.3: Slave mode control

– TS[2:0] bit definitions in Section 19.6.3: Slave mode control

– Section 17.4.6: Synchronization between TIM1, TIM5 and TIM6

timers: replaced “TS = 001 in the TIMx_SMCR register” with “see

TS[2:0] bit definitions in TIMx_SMCR register.

– Section 23.4: Operating modes: added a note about PG0 port,

– the Disclaimer.

Table 79. Document revision history (continued)

Date

Revision

Changes

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