STM8S datasheet(463/467 Pages) STMICROELECTRONICS

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DocID14587 Rev 14

463/467

RM0016

Revision history

463

23-Sep-2015

Window watchdog (WWDG)

– Corrected the downcounter bit number in Figure 28: Watchdog

block diagram

Inter-integrated circuit (I2C) interface

– Removed PEC calculation and PEC register boxes in Figure 101:

I2C block diagram.

Universal asynchronous receiver transmitter (UART)

– Updated the LIN version in Section 22.1: Introduction:

Controller area network (beCAN)

– Improved the readability of Figure 148 to Figure 151.

25-Jul-2017

– Updated the introduction of the Section 22.4.3: Slave mode with

automatic resynchronization enabled.

– Updated Section 5.3: SWIM modes.

– All figures of the document were updated (format update, no

content update). Below figures were redrawn: Figure 13,

Figure 14, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29,

Figure 34 and Figure 37.

– For the whole document, chapter titles were updated to be more

specific about their content whenever it was relevant.

04-Oct-2017

Updated:

– Section 6.2.2: Interrupt sources

– Figure 13: Interrupt processing flowchart

– Figure 15: Concurrent interrupt management

– Figure 16: Nested interrupt management

– Figure 100: I2Cbus protocol

– Figure 105: Method 1: transfer sequence diagram for master

receiver

– Figure 106: Method 2: transfer sequence diagram for master

receiver when N >2

– Figure 107: Method 2: transfer sequence diagram for master

receiver when N=2

– Figure 108: Method 2: transfer sequence diagram for master

receiver when N=1

Table 79. Document revision history (continued)

Date

Revision

Changes

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