STM8S datasheet(256/467 Pages) STMICROELECTRONICS

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8-bit basic timer (TIM4, TIM6)

RM0016

256/467

DocID14587 Rev 14

19.6.2

Control register 2 (TIM6_CR2)

Address offset: 0x01

Reset value: 0x00

Note:

This register is not available in TIM4.

19.6.3

Slave mode control register (TIM6_SMCR)

Address offset: 0x02

Reset value: 0x00

Note:

This register is not available in TIM4.

654

3210

Reserved

MMS[2:0]

Reserved

rrw

Bit 7 Reserved, must be kept cleared

Bits 6:4 MMS[2:0]: Master mode selection

These bits are used to select the information to be sent in master mode to for synchronization

(TRGO). The combination is as follows:

000: Reset - the UG bit from the TIM6_EGR register is used as a trigger output (TRGO). If the reset

is generated by the trigger input (clock/trigger mode controller configured in trigger reset mode), the

signal on the TRGO is delayed compared to the actual reset.

001: Enable - the counter enable signal is used as a trigger output (TRGO). It is used to start several

timers at the same time or to control a window in which a slave timer is enabled. The counter enable

signal is generated by a logic OR between the CEN control bit and the trigger input when configured

in gated mode. When the counter enable signal is controlled by the trigger input, there is a delay on

TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIM6_SMCR

010: Update - The update event is selected as trigger output (TRGO)

011: Reserved

100: Reserved

101: Reserved

111: Reserved

Bits 3:0 Reserved, must be kept cleared

654

3210

MSM

TS[2:0]

Reserved

SMS[2:0]

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