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STM8S 데이터시트(PDF) 259 Page - STMicroelectronics |
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STM8S 데이터시트(HTML) 259 Page - STMicroelectronics |
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259 / 467 page ![]() DocID14587 Rev 14 259/467 RM0016 8-bit basic timer (TIM4, TIM6) 261 19.6.6 Event generation register (TIMx_EGR) Address offset: 0x03 or 0x05 (TIM4), 0x05 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 19.6.7 Counter (TIMx_CNTR) Address offset: 0x04 or 0x06 (TIM4), 0x06 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 19.6.8 Prescaler register (TIMx_PSCR) Address offset: 0x05 or 0x07 (TIM4), 0x07 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 7 654 3210 Reserved TG Reserved UG w w Bit 7 Reserved, must be kept cleared Bit 6 TG: Trigger generation This bit is set by software to generate an event. It is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIM6_SR register. An interrupt is generated if enabled by the TIE bit Note: In TIM4 this bit is reserved. Bits 5:1 Reserved, must be kept cleared Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initializes the counter and generates an update of the registers. Note that the prescaler counter is also cleared. 7 654 3210 CNT[7:0] rw rw rw rw rw rw rw rw Bits 7:0 CNT[7:0]: Counter value 7 654 3210 Reserved PSC[2:0] rw rw rw |
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