STM8S datasheet(358/467 Pages) STMICROELECTRONICS

358 / 467 page

Universal asynchronous receiver transmitter (UART)

RM0016

358/467

DocID14587 Rev 14

Note:

Deviation checking is based on the current baudrate and not on the nominal one. Therefore,

in order to guarantee correct deviation checking, the baudrate generator must reload the

nominal value before each new Break reception. This nominal value is programmed by the

application during initialization. To do this software must set the LDUM bit before checksum

reception.

If LDUM bit is set, the next character reception will automatically reload the baudrate

generator with nominal value.

You can also reload the nominal value by writing to BRR2 and BRR1. This second method

is typically used when an error occurs during response transmission or reception.

If for any reason, the LDUM bit is set when UART is receiving a new Break and a Synch

Field, this bit will be ignored and cleared. UART will adjust the baudrate generator with a

value calculated from the synch field.

LIN header error detection

LHE is set if one of the following conditions occurs:

•

Break Delimiter is too short

•

Deviation error on the Synch Field is outside the LIN specification which allows up to +/

-14% of period deviation between the slave and master oscillators.

•

Framing error in Synch Field or Identifier Field

•

A LIN header reception time-out

•

An overflow during the Synch Field Measurement, which leads to an overflow of the

divider registers

LIN header time-out error

The description in the section LIN header time-out error on page 354 applies also when

automatic resynchronization is enabled.

UART clock tolerance when synchronized

When synchronization has been performed, following reception of a LIN Break, the UART

has the same clock deviation tolerance as in UART mode, which is explained below:

During reception, each bit is oversampled 16 times. The mean of the 8th, 9th and 10th

samples is considered as the bit value.

Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one

start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%.

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