STM8S datasheet(359/467 Pages) STMICROELECTRONICS

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RM0016

Universal asynchronous receiver transmitter (UART)

377

UART clock tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no characters have been transmitted for a

relatively long time), the maximum tolerated deviation of the UART clock is +/-14%.

If the deviation is within this range then the LIN Break is detected properly when a new

reception occurs.

This is made possible by the fact that masters send 13 low bits for the LIN Break, which can

be interpreted as 11 low bits (13 bits -14% = 11.18) by a "fast" slave and then considered as

a LIN Break. According to the LIN specification, a LIN Break is valid when its duration is

greater than tSBRKTS = 10. This means that the LIN Break must last at least 11 low bits.

If the period desynchronization of the slave is +14% (slave too slow), the character "00h"

which represents a sequence of 9 low bits must not be interpreted as a break character (9

bits + 14% = 10.26). Consequently, a valid LIN break must last at least 11 low bits.

Clock deviation causes

The causes which contribute to the total deviation are:

•

DTRA: Deviation due to transmitter error. Note: the transmitter can be either a master

or a slave (in case of a slave listening to the response of another slave).

•

DMEAS: Error due to the LIN Synch measurement performed by the receiver.

•

DQUANT: Error due to the baud rate quantization of the receiver.

•

DREC: Deviation of the local oscillator of the receiver: This deviation can occur during

the reception of one complete LIN message assuming that the deviation has been

compensated at the beginning of the message.

•

DTCL: Deviation due to the transmission line (generally due to the transceivers)

•

All the deviations of the system should be added and compared to the UART clock

tolerance:

–

DTRA + DMEAS+ DQUANT + DREC + DTCL < 3.75%

Error due to LIN synch measurement

The LIN Synch Field is measured over eight bit times.

This measurement is performed using a counter clocked by the CPU clock. The edge

detections are performed using the CPU clock cycle.

This leads to a precision of 2 CPU clock cycles for the measurement which lasts

8*UARTDIV clock cycles.

Consequently, this error (DMEAS) is equal to:

2 / (8*UARTDIVMIN)

UARTDIVMIN corresponds to the minimum LIN prescaler content, leading to the maximum

baud rate, taking into account the maximum deviation of +/-14%.

Error due to baud rate quantization

The baud rate can be adjusted in steps of 1 / (UARTDIV). The worst case occurs when the

"real" baud rate is in the middle of the step.

This leads to a quantization error (DQUANT) equal to 1 / (2*UARTDIVMIN).

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