ATM90E32AS-AU-R datasheet(29/84 Pages) ATMEL

29 / 84 page

M90E32AS [DATASHEET]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

3.9.2

DELAY/PHASE BASED COMPENSATION

The Channel phase compensation delay can be tuned according to the measured frequency and current RMS.

•

Phi0 is the calibrated delay between the V/I channel (in terms of 2.048Mhz clock cycles)

•

PhiF is the delay change per frequency change

•

F0 is the nominal frequency,

•

PhiIrms is the delay change per current change

•

Phi_offset is the offset for segment calibration

•

Log(x)= Log2(x)*16

If (Irms > Irms0)

PhiIrms = PhiIrms0, Irms_ref = Irms0,

Phi_offset=0

If (Irms1<Irms < Irms0)

PhiIrms= PhiIrms1, Irms_ref = Irms0,

Phi_offset=0

If (Irms < Irms1)

PhiIrms = PhiIrms2, Irms_ref = Irms1,

Implementation Note:

The channel_phi could be computed at the 8Khz rate. The computed channel_phi (before applied to the delay chain in the

decimator) shall be averaged and updated every 8192 8Khz-samples (about one update per second). This is to attenuate

the fluctuation generated in the computation when the current is small and avoid frequent updating of the delay, which is

assumed to be a fixed value in the decimator.

Phi_offset

256

))

Irms_ref

Irms

(Log(

PhiIrms

512

F0)

PhiF

Phi0

Channel_Ph

256

))

Irms0

Irms1

(Log(

PhiIrms1

Phi_offset

ATM90E32AS-AU-R 데이터시트(PDF) 29 Page - ATMEL Corporation

ATM90E32AS-AU-R 데이터시트(HTML) 29 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

데이터시트 다운로드

링크 URL