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VSC8221 데이터시트(PDF) 38 Page - Microsemi Corporation

부품명 VSC8221
상세설명  Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs
PDF  138 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8221 데이터시트(HTML) 38 Page - Microsemi Corporation

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VSC8221
Data Sheet
VMDS-10106 Revision 4.1
December 2006
38 of 40
40
12.1.4 Read Operation - Sequential Read
• R4..R0 are the 5 bits of the Register address
• M7..M0 are bits of the Upper byte of the 16 bit Register data
• L7..L0 are bits of the Lower byte of the 16 bit Register data
12.2 PHY Register Access with SMi in iEEE Mode
in iEEE mode, the SMi is fully compliant with the iEEE 802.3-2000 Mii interface specifications.
in iEEE mode, the SMi pins function as follows:
As many as 32 PHYs (32 distinct PHY Addresses) can share a common iEEE SMi signal pair (MDC, MDiO).
Table 18. SMi Pin Descriptions - iEEE Mode
Pin Name
Description
MDC
Clock input, 0 – 12.5 Mhz.
MDiO
Bidirectional Data. This pin should be pulled high on the board using a 4.7k
Ω to
10k
Ω resistor.
MDiNT
Active Low or Active High open drain interrupt output.
S
0
0
0
A
0
0
1
1
0
1
0
1
H
A
R0
R1
R2
R3
R4
M0
M1
M2
M3
M4
M5
M6
M7
T
N
L0
L1
L2
L3
L4
L5
L6
L7
From Host to PHY/Receiver
From PHY/Receiver to Host
S
A
1
0
1
1
0
1
0
1
H
L0
L1
L2
L3
L4
L5
L6
L7
H
M0
M1
M2
M3
M4
M5
M6
M7
H
L0
L1
L2
L3
L4
L5
L6
L7
H
M0
M1
M2
M3
M4
M5
M6
M7
MSB for Register R
LSB for Register R+n
LSB for Register R+n
LSB for Register R+1
MSB for Register R+1
LSB for Register R



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