VSC8221 datasheet(61/138 Pages) MICROSEMI

61 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

61 of 61

20 PHY STARTUP AND INITIALIZATION

The PHY Startup and initialization sequence is detailed in the flowchart below.

Figure 22. PHY Startup and initialization Sequence

Start - 3.3v supply is up

If RESETz=1

Is external 1.2v

supply up

Latch EEDAT,PLLMODE,OSCDISz and MDINTz

polarity using internally generated rising edge

Is REFCLK

input present

1.Perfom Hardware Initialization - i.e. overwrite

default PHY Register values based on resister

values on CMODE[3:0]

2.Store startup CMODE initialization values

3. Set Internal variable SR=0.

Perform EEPROM Initialization - i.e. overwrite

default PHY Register values using configuration

EEPROM data

If EEDAT=1

Is TXDIS/SRESETz deasserted

(The assertion polarity is based on

setting of Extended MII register

21E.15, which can be initialized

using Hardware or EEPROM

Initialization)

Drive out CLKOUT and CLKOUTMICRO if

enabled during Initialzation.

Start - 3.3v supply is up

If RESETz=0

NORMAL STATE

Is TXDIS/

SRESETz

asserted

If MII Register 22.9 ‘Sticky Reset Enable’=0

(On RESETz deassertion this bit will be set to 1)

If Extended MII Register 21E.14 ‘Reread

EEPROM on s/w reset’=1

(On RESETz deassertion this bit will be set to 0)

If SR=1

1.Perfom Initialization - i.e. overwrite

default PHY Register values based on stored

CMODE values.

Perform EEPROM Initialization - i.e. overwrite

default PHY Register values using configuration

EEPROM data

If EEDAT=1

SR=1

1. Enter Normal Operating Mode

2. Release SMI for user access.

NORMAL STATE

If REGEN=1

1. Turn on on-chip

regulator and wait for

1.2v supply to come up.

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