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STM32H723VG 데이터시트(PDF) 114 Page - STMicroelectronics |
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STM32H723VG 데이터시트(HTML) 114 Page - STMicroelectronics |
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114 / 227 page ![]() Electrical characteristics STM32H723xE/G 114/227 DS13313 Rev 2 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. Table 40. PLL2 and PLL3 characteristics (wide VCO frequency range)(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % fPLL_OUT PLL multiplier output clock P, Q, R VOS0 1.5 - 550(2) MHz VOS1 1.5 - 400(2) VOS2 1.5 - 300(2) VOS3 1.5 - 170(2) fVCO_OUT PLL VCO output - 192 - 960(3) tLOCK PLL lock time Normal mode - 50 150(3) µs Sigma-delta mode (fPLL_IN ≥ 8 MHz) -58 166(3) Jitter Cycle-to-cycle jitter(4) fVCO_OUT = 192 MHz - 134 - ±ps fVCO_OUT = 200 MHz - 134 - fVCO_OUT = 400 MHz - 76 - fVCO_OUT = 800 MHz - 39 - Long term jitter Normal mode (fPLL_IN = 2 MHz) fVCO_OUT = 560 MHz -±0.2 - % Normal mode (fPLL_IN = 16 MHz) fVCO_OUT = 560 MHz -±0.8 - Sigma-delta mode (fPLL_IN = 2 MHz) fVCO_OUT = 560 MHz -±0.2 - Sigma-delta mode (fPLL_IN = 16 MHz) fVCO_OUT = 560 MHz -±0.8 - IDD(PLL)(3) PLL power consumption fVCO_OUT = 836 MHz VDD - 590 1500 µA VCORE -720 - fVCO_OUT = 192 MHz VDD -180 600 VCORE -280 - 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. |
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