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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32H723VG 데이터시트(PDF) 115 Page - STMicroelectronics |
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STM32H723VG 데이터시트(HTML) 115 Page - STMicroelectronics |
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115 / 227 page  DS13313 Rev 2 115/227 STM32H723xE/G Electrical characteristics 208 3. Guaranteed by characterization results. 4. Integer mode only. Table 41. PLL2 and PLL3 characteristics (medium VCO frequency range)(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % fPLL_OUT PLL multiplier output clock P, Q, R VOS0 1.17 - 210 MHz VOS1 1.17 - 210 - VOS2 1.17 - 210 - VOS3 1.17 - 200 - fVCO_OUT PLL VCO output - 150 - 420 - tLOCK PLL lock time Normal mode - 60 100(2) µs Sigma-delta mode forbidden Jitter Cycle-to-cycle jitter(3) fVCO_OUT = 150 MHz - 145 - ±ps fVCO_OUT = 200 MHz - 91 - fVCO_OUT = 400 MHz - 64 - fVCO_OUT = 420 MHz - 63 - Period jitter fPLL_OUT = 50 MHz fVCO_OUT = 150 MHz -55- ±ps fVCO_OUT = 400 MHz - 30 - Long term jitter Normal mode fVCO_OUT = 400 MHz -±0.3- % IDD(PLL) PLL power consumption on VDD fVCO_OUT = 420 MHz VDD - 440 1150 µA VCORE -530 - fVCO_OUT = 150 MHz VDD - 180 500 VCORE -200 - 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. |
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