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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VS6624P0LP 데이터시트(PDF) 93 Page - STMicroelectronics |
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VS6624P0LP 데이터시트(HTML) 93 Page - STMicroelectronics |
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93 / 100 page  VS6624 Electrical characteristics Rev 1 93/100 13.7 Parallel data interface timing VS6624 contains a parallel data output port (D[7:0]) and associated qualification signals (HSYNC, VSYNC, PCLK and FSO). This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 35. Parallel data output video timing tPCLKL tPCLKH 1/fPCLK PCLK D[0:7] HSYNC, polarity = 0 tDV Valid VSYNC Table 50. Parallel data interface timings Symbol Description Conditions Min. Typ. Max. Unit fPCLK PCLK frequency 54 MHz tPCLKL PCLK low width ns tPCLKH PCLK high width ns tDV PCLK to output valid ns |
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