VS6624P0LP datasheet(27/100 Pages) STMICROELECTRONICS

27 / 100 page

VS6624

Data synchronization methods

Rev 1

27/100

Figure 11. ITU656 frame structure with even codes

The synchronization codes for odd and even frames are listed in

Table 3 and Table 4. By

default all frames output from the VS6624 are EVEN. It is possible to set all frames to be

ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in

the

Output formatter control register bank.

Table 3.

ITU656 embedded synchronization code definition (even frames)

Name

Description

4-byte sequence

SAV

Line start - active

FF 00 00 80

EAV

Line end - active

FF 00 00 9D

SAV (blanking)

Line start - blanking

FF 00 00 AB

EAV (blanking)

Line end - blanking

FF 00 00 B6

Table 4.

ITU656 embedded synchronization code definition (odd frames)

Name

Description

4-byte sequence

SAV

Line start - active

FF 00 00 C7

EAV

Line end - active

FF 00 00 DA

SAV (blanking)

Line start - blanking

FF 00 00 EC

EAV (blanking)

Line end - blanking

FF 00 00 F1

EAV

SAV

Frame of image data

Line 1

Line 480

Frame blanking period

EAV

SAV

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