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SH7041A 데이터시트(PDF) 368 Page - Renesas Technology Corp

부품명 SH7041A
상세설명  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A 데이터시트(HTML) 368 Page - Renesas Technology Corp

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Input Capture Operation: Figure 12.14 shows input capture. The falling edge of TIOCB and
both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to
clear at the input capture of the TGRB register.
Counter cleared
by TIOCB input
(falling edge)
TCNT value
H'0180
H'0160
H'0005
H'0010
H'0000
TIOCB
TIOCA
TGRA
TGRB
H'0005
H'0160
H'0010
H'0180
Time
Figure 12.14 Input Capture Operation
12.4.3
Synchronous Operation
In the synchronizing mode, two or more timer counters can be rewritten simultaneously
(synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR
settings (synchronized clear).
The synchronizing mode can increase the number of TGR registers for a single time base. All five
channels can be set for synchronous operation.



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