SH7041A datasheet(371/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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12.4.4

Buffer Operation

Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer

registers. Table 12.5 shows the register combinations for buffer operation.

Table 12.5

Channel

General Register

Buffer Register

TGR0A

TGR0C

TGR0B

TGR0D

TGR3A

TGR3C

TGR3B

TGR3D

TGR4A

TGR4C

TGR4B

TGR4D

The buffer operation differs, depending on whether the TGR has been set as an input capture

When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding

channel buffer register value is transferred to the general register. Figure 12.17 shows an example.

Compare match signal

Buffer

TCNT

Comparator

General

Figure 12.17 Compare Match Buffer Operation

When TGR Is an Input Capture Register: When an input capture occurs, the timer counter

(TCNT) value is transferred to the general register (TGR), and the value that had been held up to

that time in the TGR is transferred to the buffer register (figure 12.18).

Input capture signal

TCNT

Buffer

General

Figure 12.18 Input Capture Buffer Operation

SH7041A 데이터시트(PDF) 371 Page - Renesas Technology Corp