 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
SH7041A 데이터시트(PDF) 599 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7041A 데이터시트(HTML) 599 Page - Renesas Technology Corp |
|
|
599 / 923 page  561 15.4.9 A/D Conversion Time The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D converter samples the input at time t D after the ADST bit is set to 1, and then starts the conversion. The A/D conversion time t CONV is the sum of the conversion start delay time tD, the input sampling time t SPL, and the operating time tCP. This conversion time is not a set value, but is decided by the t D ADCSR write timing, or the timer conversion start trigger generation timing. Figure 15.13 shows an example of A/D conversion timing. Table 15.7 lists A/D conversion times. Address Write signal ADST Sampling timing φ ADF tD tCONV tSPL tCP t D: t SPL: t CONV: t CP: A/D conversion start delay time Input sampling time A/D conversion time Operation time Figure 15.13 A/D Conversion Timing |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
