SH7041A datasheet(595/923 Pages) RENESAS

595 / 923 page

557

15.4.7

Conversion Start Modes

The conversion start mode of the high speed A/D converter is set by the PWR bit of the ADCSR.

When the PWR bit is cleared to 0, low-power conversion mode is set and the internal analog

circuit becomes inactive. High-speed start mode is set by setting the PWR bit to 1, and the analog

circuit becomes active.

In the low-power conversion mode, power is applied to the analog circuitry simultaneous to the

conversion start (ADST set). When 200 cycles of the reference clock have elapsed, conversion

becomes possible for the analog circuit and the first A/D conversion begins. When performing

consecutive conversions, the second and later conversions are executed in 10 cycles. Select the

basic clock with the CKS bit of the ADCSR. When the A/D conversion ends, ADST is cleared to

0 and the analog circuit power supply is automatically cut off. Because the analog circuit is only

active during the A/D conversion operation period in this mode, current consumption can be

reduced.

In high-speed start mode, ADST is cleared to 0 when A/D conversion ends. Power continues to be

supplied to the analog circuitry, and conversion-ready status is maintained. Conversion is restarted

immediately by resetting ADST to 1. However, the first conversion after power-on begins 200

cycles after setting ADST. Clear the PWR bit to 0 to switch off the analog power supply. When

performing consecutive conversions, the second and later conversions are executed in 20 cycles.

Because the analog circuit is always active in this mode, A/D conversion can be executed at high

speed.

SH7041A 데이터시트(PDF) 595 Page - Renesas Technology Corp