| 전자부품 데이터시트 검색엔진 |
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SH7041A 데이터시트(PDF) 732 Page - Renesas Technology Corp |
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SH7041A 데이터시트(HTML) 732 Page - Renesas Technology Corp |
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732 / 923 page ![]() 694 • Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or release (applicable addresses: H'20000–H'3FFFF). Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3: EV2 Description 0 Erase verify mode release (Initial value) 1 Transition to the erase verify mode [Setting condition] When FWE=1 and SWE=1 • Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or release (applicable addresses: H'20000–H'3FFFF). Do not set the ESU2, PSU2, EV2, E2, or P2 bit at the same time. Bit 2: PV2 Description 0 Program verify mode release (Initial value) 1 Transition to the program verify mode [Setting condition] When FWE=1, and SWE=1 • Bit 1—Erase 2 (E2): Selects erase mode transition or release (applicable addresses: H'20000– H'3FFFF). Do not set the ESU2, PSU2, EV2, PV2, or P2 bit at the same time. Bit 1: E2 Description 0 Erase mode release (Initial value) 1 Transition to the erase mode [Setting condition] When FWE=1, SWE=1, and ESU2=1 • Bit 0—Program 2 (P2): Selects program mode transition or release (applicable addresses: H'20000–H'3FFFF). Do not set the ESU2, PSU2, EV2, PV2, or E2 bit at the same time. Bit 0: P2 Description 0 Program mode release(Initial value) 1 Transition to the program mode [Setting condition] When FWE=1, SWE=1, and PSU2=1 |
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