SH7041A datasheet(734/923 Pages) RENESAS

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Table 22.4

Flash Memory Erase Blocks

Block (size)

Addresses

EB0 (32kB)

H'000000–H'007FFF

EB1 (32kB)

H'008000–H'00FFFF

EB2 (32kB)

H'010000–H'017FFF

EB3 (32kB)

H'018000–H'01FFFF

EB4 (32kB)

H'020000–H'027FFF

EB5 (32kB)

H'028000–H'02FFFF

EB6 (32kB)

H'030000–H'037FFF

EB7 (28kB)

H'038000–H'03EFFF

EB8 (1kB)

H'03F000–H'03F3FF

EB9 (1kB)

H'03F400–H'03F7FF

EB10 (1kB)

H'03F800–H'03FBFF

EB11 (1kB)

H'03FC00–H'03FFFF

22.5.5

RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset. It is

not initialized in software standby mode. RAMER settings should be made in user mode or user

program mode. (For details, see the description of the BSC.)

Flash memory area divisions are shown in table 22.5. To ensure correct operation of the emulation

function, the ROM for which RAM emulation is performed should not be accessed immediately

after this register has been modified. Normal execution of an access immediately after register

modification is not guaranteed.

Bit:

——

———

—

Initial value:

R/W:

Bit:

—

RAMS

RAM1

RAM0

Initial value:

R/W:

R/W

• Bits 15–3—Reserved bits: These bits are always read as 0.

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