SH7041A datasheet(743/923 Pages) RENESAS

743 / 923 page

705

FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set

200 µs as the time for one programming operation.

22.7.2

Program-Verify Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses

H'20000–H'3FFFF)

In program-verify mode, the data written in program mode is read to check whether it has been

correctly written in the flash memory.

After the elapse of a given programming time, the programming mode is exited (the Pn bit in

FLMCRn is released, then the PSUn bit is released at least 10 µs later). The watchdog timer is

released after the elapse of 10 µs or more, and the operating mode is switched to program-verify

mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write

of H'FF data should be made to the addresses to be read. The dummy write should be executed

after the elapse of 4 µs or more. When the flash memory is read in this state (verify data is read in

32-bit units), the data at the latched address is read. Wait at least 2 µs after the dummy write

before performing this read operation. Next, the written data is compared with the verify data, and

reprogram data is computed (see figure 22.13) and transferred to the reprogram data area. After 32

bytes of data have been verified, exit program-verify mode, wait for at least 4 µs, then release the

SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the

program/program-verify sequence as before. However, ensure that the program/program-verify

sequence is not repeated more than 1,000 times on the same bits.

SH7041A 데이터시트(PDF) 743 Page - Renesas Technology Corp