SH7041A datasheet(241/923 Pages) RENESAS

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10.6.2

Simplification of Bus Cycle Start Detection

For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles

designated by the CW3–CW0 bits of the BCR2 occur. However, for write cycles after reads, the

number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits.

When idle cycles already exist between access cycles, waits are not inserted. Figure 10.21 shows

an example. A continuous access idle is specified for CSn space, and CSn space is consecutively

write accessed.

CSn

WRx

Data

CSn space access

Idle cycle

Address

Tidle

Figure 10.21 Same Space Consecutive Access Idle Cycle Insertion Example

10.7

Bus Arbitration

The SH7040 series has a bus arbitration function that, when a bus release request is received from

an external device, releases the bus to that device. It also has two internal bus masters, the CPU

and the DMAC, DTC. The priority ranking for determining bus right transfer between these bus

masters is:

Bus right request from external device > refresh > DTC > DMAC > CPU

However, during a read or write in DMAC dual address mode, a burst transfer, or indirect address

transfer mode operation, the DMAC continues operating even if a DTC request is received.

Through port register settings,

IRQOUT is asserted to indicate that a CAS-before-RAS refresh

request for DRAM has been generated during release of bus rights to an external device. Use this

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