SH7041A datasheet(237/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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10.5

Address/Data Multiplex I/O Space Access

When the BCR1 register IOE bit is set to 1, the D15–D0 pins can be used for multiplexed

address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data

multiplexing can be directly connected to this LSI.

Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0

and 16 bit when A14 = 1.

10.5.1

Basic Timing

When the IOE bit of the BCR1 is set to 1, CS3 space becomes address/data multiplex I/O space.

When this space is accessed, addresses and data are multiplexed. When the A14 address bit is 0,

the bus size becomes 8 bit and addresses and data are input and output through the D7–D0 pins.

When the A14 address bit is 1, the bus size becomes 16 bit and address output and data I/O occur

through the D15–D0 pins. Access for the address/data multiplex I/O space is controlled by the

AH, RD, and WRx signals.

Address/data multiplex I/O space accesses are done after a 3-cycle (fixed) address output, as an

ordinary space type access (figure 10.17).

CS3

Data

WRx

Data

Address

Ta1

Ta2

Ta3

Ta4

Read

Write

Address output

Data output

Data input

Figure 10.17 Address/Data Multiplex I/O Space Access Timing (No Waits)

SH7041A 데이터시트(PDF) 237 Page - Renesas Technology Corp