SH7041A datasheet(322/923 Pages) RENESAS

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Channels 0, 3, 4:

Bit 7:

CCLR2

Bit 6:

CCLR1

Bit 5:

CCLR0

Description

TCNT clear disabled (initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match or input capture

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync.*

TCNT clear disabled

TCNT is cleared by TGRC compare-match or input capture*

TCNT is cleared by TGRD compare-match or input capture*

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync*

Notes: *1 Setting the SYNC bit of the TSYR to 1 sets the synchronization.

*2 When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because

the buffer registers have priority and compare-match/input captures do not occur.

Channels 1, 2:

Bit 7:

Reserved*

Bit 6:

CCLR1

Bit 5:

CCLR0

Description

TCNT clear disabled (initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match or input capture

Synchronizing clear: TCNT is cleared in synchronization with

clear of other channel counters operating in sync*

Notes: *1 The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified.

*2 Setting the SYNC bit of the TSYR to 1 sets the synchronization.

• Bits 4–3—Clock Edge 1, 0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select the input clock

edges. When counting is done on both edges of the internal clock the input clock frequency

becomes 1/2 (Example: both edges of

φ/4 = rising edge of φ/2). When phase count mode is

used with channels 1, 2, these settings are ignored, as the phase count mode settings have

priority.

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