 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST25R3911B 데이터시트(PDF) 24 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST25R3911B 데이터시트(HTML) 24 Page - STMicroelectronics |
|
|
24 / 116 page  Figure 16. SPI communication: direct command chaining /SS Direct command Read, Write or FIFO Mode SPI timing Table 7. SPI timing Symbol Parameter Min Typ Max Unit Comments General timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C) TSCLK SCLK period 167 - - ns TSCLK=TSCLKL+TSCLKH, use of shorter SCLK period may lead to incorrect FIFO operation. TSCLKL SCLK low 70 - 1 - TSCLKH SCLK high 70 - - - TSSH SPI reset (/SS high) 100 - - - TNCSL /SS falling to SCLK rising 25 - - First SCLK pulse TNCSH SCLK falling to /SS rising 300 - - Last SCLK pulse TDIS Data in set-up time 10 - - - TDIH Data in hold time 10 - - - Read timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C, CLOAD ≤ 50 pF) TDOD Data out delay - 20 - ns - TDOHZ Data out to high impedance delay - 20 - - Figure 17. SPI general timing ... ... ... DATAI DATAI DATAI ... tSCLKH tNCSL tSCLKL tDIS tDIH tNCSH /SS MOSI MISO SCLK ST25R3911B Application information DS11793 - Rev 6 page 24/116 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
