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ADL5569BCPZ-R7 데이터시트(PDF) 15 Page - Analog Devices |
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ADL5569BCPZ-R7 데이터시트(HTML) 15 Page - Analog Devices |
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15 / 23 page ![]() Data Sheet ADL5569 Rev. C | Page 15 of 23 APPLICATIONS INFORMATION BASIC CONNECTIONS Figure 39 shows the basic connections for operating the ADL5569. Apply 5 V to the VCC and VCC2 pins and decouple with 0.1 µF and 10 µF surface-mount ceramic capacitors in parallel to ground. Decouple the VCOM and VCOM2 pins (Pin 7 and Pin 15) using a 0.1 µF capacitor. The PDB and PDB2 pins (Pin 6 and Pin 16) are tied to logic high, respectively, to enable each amplifier. A differential signal is applied to Amplifier 1 through Pin 1 (VIN) and Pin 2 (VIP) and to Amplifier 2 through Pin 4 (VIP2) and Pin 5 (VIN2). Each amplifier has a gain of 20 dB. The Amplifier 1 input pins, Pin 1 (VIN) and Pin 2 (VIP), and the output pins, Pin 13 (VON) and Pin 12 (VOP), are biased by applying a voltage to Pin 15 (VCOM). If VCOM is left open, VCOM equals ½ of VS. The Amplifier 2 input pins, Pin 4 (VIP2) and Pin 5 (VIN2), and the output pins, Pin 9 (VON2) and Pin 10 (VOP2), are biased by applying a voltage to Pin 7 (VCOM2). If VCOM2 is left open, VCOM2 equals ½ of VS. The ADL5569 can be ac-coupled, as shown in Figure 39, or it can be dc-coupled if within the specified input and output common-mode voltage ranges. Pulling the PDB and PDB2 pins low puts the ADL5569 in sleep mode, reducing the current consumption to 16 mA at ambient temperature. 0.01µF BALANCED LOAD VIP VIN 0.01µF VOP VCOM VON 0.01µF VCC2 21 18 18 18 17 2 1 PDB PDB2 3.3V 0.01µF 0.01µF 3.3V 2 15 12 8 13 1 16 6 VCC ADL5569 14 11 3 0.01µF 10µF VS 0.01µF EXPOSED PAD + ½ RS ½ RS BALANCED AC 0.01µF BALANCED LOAD VIP2 VIN2 0.01µF VOP2 VCOM2 VON2 0.01µF 21 18 17 0.01µF 0.01µF 4 7 10 9 5 ½ RS ½ RS BALANCED AC 50Ω RG 500Ω RF GM B 50Ω RG 500Ω RF 50Ω RG 500Ω RF GM B 50Ω RG 500Ω RF Figure 39. Basic Connections |
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