VSC8540RT datasheet(28/87 Pages) MICROCHIP

28 / 87 page

VSC8540RT

DS60001603E-page 28

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5.10.1

SMI FRAMES

Data is transferred over the SMI using 32-bit frames with an optional, arbitrary-length preamble. Before the first frame

can be sent, at least two clock pulses on MDC must be provided with the MDIO signal at logic one to initialize the SMI

state machine. The following illustrations show the SMI frame format for read and write operations.

FIGURE 5-12:

SMI READ FRAME

FIGURE 5-13:

SMI WRITE FRAME

The following list defines the terms used in the SMI read and write timing diagrams.

• Idle—During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up resistor to pull

the MDIO node up to a logical 1 state. Because the idle mode does not contain any transitions on MDIO, the num-

ber of bits is undefined during idle.

• Preamble—By default, preambles are not expected or required. The preamble is a string of ones. If it exists, the

preamble must be at least 1 bit; otherwise, it can be of an arbitrary length.

• Start of Frame Delimiter (SFD—A pattern of 01 indicates the start of frame. If the pattern is not 01, all following

bits are ignored until the next preamble pattern is detected.

• Read or Write Opcode—A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits are not either

01 or 10, all following bits are ignored until the next preamble pattern is detected.

• PHY Address—The particular VSC8540RT device responds to a message frame only when the received PHY

address matches its physical address. The physical address is 5 bits long (4:0).

• Register Address—The next five bits are the register address.

• Turnaround—The two bits used to avoid signal contention when a read operation is performed on the MDIO are

called the turnaround (TA) bits. During read operations, the VSC8540RT device drives the second TA bit, a logical

• Data—The 16-bits read from or written to the device are considered the data or data stream. When data is read

from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge of MDC. When data is writ-

ten to the PHY, it must be valid around the rising edge of MDC.

• Idle—The sequence is repeated.

5.10.2

SMI INTERRUPT

The SMI includes an interrupt signal, MDINT, for signaling the station manager when certain events occur in the

VSC8540RT device.

MDIO

Idle Preamble

(optional)

SFD

Read

MDC

Station manager drives MDIO

PHY drives MDIO

PHY Address

to PHY

from PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

MDIO

Idle Preamble

(optional)

SFD

Write

MDC

Station manager drives MDIO (PHY tri-states MDIO during the entire sequence)

PHY Address

to PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

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