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VSC8540RT 데이터시트(PDF) 9 Page - Microchip Technology

부품명 VSC8540RT
상세설명  Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces
PDF  87 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

VSC8540RT 데이터시트(HTML) 9 Page - Microchip Technology

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 2022 Microchip Technology Inc. and its subsidiaries
DS60001603E-page 9
VSC8540RT
Miscellaneous
REF_FILT_A
67
A
VDD25A
Reference filter connects to an external
0.01 uF (20%) capacitor to analog
ground
Miscellaneous
REF_REXT_A
1
A
VDD25A
Reference connects to an external 2k Ω
(1%) resistor to analog ground
Miscellaneous
RESERVED_0
66
VDD25A
Reserved signal, leave unconnected
Miscellaneous
RESERVED_1
65
VDD25A
Reserved signal, leave unconnected
Miscellaneous
RESERVED_2
7
ADIFF VDD25A
Internal test signal. Connect a 100 Ω
(5%) resistor across this pin and pin 6.
Miscellaneous
RESERVED_3
6
ADIFF VDD25A
Internal test signal. Connect a 100 Ω
(5%) resistor across this pin and pin 7.
Miscellaneous
RESERVED_4
4
ADIFF VDD25A
Internal test signal. Connect a 100 Ω
(5%) resistor across this pin and pin 3.
Miscellaneous
RESERVED_5
3
ADIFF VDD25A
Internal test signal. Connect a 100 Ω
(5%) resistor across this pin and pin 4.
Miscellaneous
RESERVED_6
47
I, PD
VDDMAC
Reserved signal, leave unconnected
Miscellaneous
RESERVED_7
46
I, PD
VDDMAC
Reserved signal, leave unconnected
Miscellaneous
RESERVED_8
45
I, PD
VDDMAC
Reserved signal, leave unconnected
Miscellaneous
RESERVED_9
43
I, PD
VDDMAC
Reserved signal, leave unconnected
Miscellaneous
RXD4
24
I/O,
PD
VDDMAC
SOF output. The logic state on this pin is
latched on the rising edge of NRESET to
configure the device. See Hardware
Mode Strapping and PHY Addressing
for details. Does not perform any GMII
function for this device.
Miscellaneous
RXD5
23
I/O,
PD
VDDMAC
SOF output. The logic state on this pin is
latched on the rising edge of NRESET to
configure the device. See Hardware
Mode Strapping and PHY Addressing
for details. Does not perform any GMII
function for this device.
Miscellaneous
RXD6
21
I/O,
PD
VDDMAC
SOF output. The logic state on this pin is
latched on the rising edge of NRESET to
configure the device. See Hardware
Mode Strapping and PHY Addressing
for details. Does not perform any GMII
function for this device.
Miscellaneous
RXD7
20
I/O,
PD
VDDMAC
SOF output. The logic state on this pin is
latched on the rising edge of NRESET to
configure the device. See Hardware
Mode Strapping and PHY Addressing
for details. Does not perform any GMII
function for this device.
TABLE 3-2:
PINS BY FUNCTION



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