VSC8540RT datasheet(51/87 Pages) MICROCHIP

51 / 87 page

 2022 Microchip Technology Inc. and its subsidiaries

DS60001603E-page 51

VSC8540RT

6.3.5

ETHERNET PACKET GENERATOR (EPG) CONTROL 1

The EPG control register provides access to and control of various aspects of the EPG testing feature. There are two

separate EPG control registers. The following table shows the settings available in the first register.

The following information applies to the EPG control number 1:

• Do not run the EPG when the VSC8540RT device is connected to a live network.

• Bit 29E1.13 (continuous EPG mode control): when enabled, this mode causes the device to send continuous

packets. When disabled, the device continues to send packets only until they reache the next 10,000-packet incre-

ment mark. They then ceases to send packets.

• The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0

through 0xFF FF FF FF FF FF.

• The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0

through 0xFF FF FF FF FF FF.

• If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared and then set

back to 1 for the change to take effect and to restart the EPG.

6.3.6

ETHERNET PACKET GENERATOR CONTROL 2

testing feature. The following table shows the settings available.

Note:

If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to 1),

that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to restart the

EPG.

TABLE 6-33:

EPG CONTROL REGISTER 1, ADDRESS 29E1 (0X1D)

Bit

Name

Access

Description

Default

EPG enable1

1. To end forced transmission of EEE LPIs from the PHY, clear the force EEE LPI bit (17E2.4) first before

clearing the EPG enable bit (29E1.15).

R/W

1: Enable EPG.

EPG run or stop

R/W

1: Run EPG.

Transmission duration

R/W

1: Continuous (sends in 10,000-packet increments).

0: Send 30,000,000 packets and stop.

12:11

Packet length

R/W

00: 125 bytes.

01: 64 bytes.

10: 1518 bytes.

11: 10,000 bytes (jumbo packet).

Interpacket gap

R/W

1: 8,192 ns.

0: 96 ns.

9:6

Destination address

R/W

Lowest nibble of the 6-byte destination address.

0001

5:2

Source address

R/W

Lowest nibble of the 6-byte destination address.

0000

Payload type

R/W

1: Randomly generated payload pattern.

0: Fixed based on payload pattern.

Bad frame check sequence

(FCS) generation

R/W

1: Generate packets with bad FCS.

0: Generate packets with good FCS.

TABLE 6-34:

EPG CONTROL REGISTER 2, ADDRESS 30E1 (0X1E)

Bit

Name

Access

Description

Default

15:0 EPG packet payload R/W

Data pattern repeated in the payload of packets gener-

ated by the EPG

0x0000

VSC8540RT 데이터시트(PDF) 51 Page - Microchip Technology

VSC8540RT 데이터시트(HTML) 51 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

데이터시트 다운로드

링크 URL