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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VSC8540RT 데이터시트(PDF) 1 Page - Microchip Technology |
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VSC8540RT 데이터시트(HTML) 1 Page - Microchip Technology |
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1 / 87 page  2022 Microchip Technology Inc. and its subsidiaries DS60001603E-page 1 VSC8540RT OVERVIEW The VSC8540RT device is a radiation tolerant single port Fast Ethernet copper PHY targeting space-constrained 10/ 100BASE-TX applications. It is designed to withstand the harsh aerospace environment with enhanced radiation per- formances, extreme temperatures, and vacuum while being highly reliable. It features integrated line-side termination to conserve board space, lower EMI, and improve system performance. Additionally, integrated RGMII timing compen- sation eliminates the need for on-board delay lines. Microchip’s EcoEthernet™ v2.0 technology supports IEEE® 802.3az Energy-Efficient Ethernet (EEE) and power-saving features to reduce power based on link state and cable reach. VSC8540RT device optimizes power consumption in all link operating speeds and features a Wake-on-LAN (WoL) power management mechanism for bringing the PHY out of a low-power state using designated magic packets. Fast link failure (FLF) indication for high availability networks identifies the onset of a link failure for 10BASE-T/ 100BASE-TX links. Potential link failure events can be more flexibly monitored using an enhanced FLF2 state machine, which goes beyond FLF indication by enabling signaling of the link potentially going down within 150 µs. The device includes recovered clock output for Synchronous Ethernet applications. Programmable clock squelch con- trol is included to inhibit undesirable clocks from propagating and to help prevent timing loops. The following illustration shows a high-level, general view of a typical VSC8540RT application. APPLICATION DIAGRAM FEATURES Superior PHY and Interface Technology • Integrated 10/100BASE-TX Ethernet copper transceiver with the industry’s only non-TDR-based VeriPHY™ cable diagnostics algorithm • Patented line driver with low EMI voltage mode architecture and integrated line-side termination resistors • Wake-on-LAN using magic packets • HP Auto-MDIX and manual MDI/MDIX support • RGMII/MII/RMII MAC interface • Jumbo frame support up to 16 Kbytes with programmable synchronization FIFOs Synchronous Ethernet and IEEE 1588 Time Stamp Support • Recovered clock output with programmable clock squelch control for G.8261 Synchronous Ethernet applications • Clock output squelch to inhibit clocks during auto-negotiation and no link status • Clause 45 registers to support IEEE 802.3bf VSC8540RT Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces |
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