VSC8540RT datasheet(10/87 Pages) MICROCHIP

10 / 87 page

VSC8540RT

DS60001603E-page 10

 2022 Microchip Technology Inc. and its subsidiaries

Miscellaneous

THERMDA

VDD25A

Thermal Diode Anode

Miscellaneous

THERMDC_VSS

VDD25A

Thermal Diode Cathode connected to

device ground. Temperature sensor

must be chosen accordingly.

PHY Configuration CLK_SQUELCH_IN 57

I, PD

VDDIO

Input control to squelch recovered clock

PHY Configuration CLKOUT

I/O,

VDDIO

Clock output, can be enabled or

disabled. Output a clock based on the

local reference clock with programmable

frequency. This pin is not active when

NRESET is asserted and is disabled by

default. When disabled, the pin is held

low. The logic state on this pin is latched

on the rising edge of NRESET to

configure

CLKOUT

output.

See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

PHY Configuration COMA_MODE

I/O,

VDDIO

When this pin is asserted high, PHY is

held in a powered down state. When de-

asserted low, PHY is powered up and

resumes normal operation. This signal is

also used to synchronize the operation

of multiple chips on the same PCB to

provide visual synchronization for LEDs

driven by separate chips.

PHY Configuration FASTLINK_FAIL

VDDIO

Fast link failure indication signal

PHY Configuration LED0

VDDIO

LED direct drive outputs. All LED pins

are active low. LED_DATA output in

serial LED mode.

PHY Configuration LED1

VDDIO

LED direct drive outputs. All LED pins

are active low. LED_CLK output in serial

LED mode.

PHY Configuration NRESET

I, PD

VDDIO

Device reset. Active low input that

powers down the device and sets all

PHY Configuration RCVRD_CLK

VDDIO

Recovered clock output, can be enabled

or disabled. Output a clock based on the

selected

active

media

with

programmable frequency. This pin is not

active when NRESET is asserted. When

disabled, the pin is held low.

PHY Configuration REFCLK_SEL_0

I, PU

VDDIO

Reference clock mode/frequency select

signal

PHY Configuration REFCLK_SEL_1

I, PU

VDDIO

Reference clock mode/frequency select

signal

PHY Configuration XTAL1

VDD25A

Crystal/single ended reference clock

input

TABLE 3-2:

PINS BY FUNCTION

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