VSC8540RT datasheet(12/87 Pages) MICROCHIP

12 / 87 page

VSC8540RT

DS60001603E-page 12

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R/GMII

RX_CLK

I/O,

VDDMAC

RGMII/MII receive clock output. The

logic state on this pin is latched on the

rising edge of NRESET to configure the

device. See Section 5.3, Hardware

Mode Strapping and PHY Addressing

for details.

R/GMII

RX_DV/RX_CTL

I/O,

VDDMAC

MII receive data valid output / RGMII

receive control output. The logic state on

this pin is latched on the rising edge of

NRESET to configure the device. See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

R/GMII

RX_ER

I/O,

VDDMAC

MII receive data error output. The logic

state on this pin is latched on the rising

edge of NRESET to configure the

device. See Section 5.3, Hardware

Mode Strapping and PHY Addressing

for details.

R/GMII

RXD0

I/O,

VDDMAC

RGMII/MII data output. The logic state

on this pin is latched on the rising edge

of NRESET to configure the device. See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

R/GMII

RXD1

I/O,

VDDMAC

RGMII/MII data output. The logic state

on this pin is latched on the rising edge

of NRESET to configure the device. See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

R/GMII

RXD2

I/O,

VDDMAC

RGMII/MII data output. The logic state

on this pin is latched on the rising edge

of NRESET to configure the device. See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

R/GMII

RXD3

I/O,

VDDMAC

RGMII/MII data output. The logic state

on this pin is latched on the rising edge

of NRESET to configure the device. See

Section 5.3, Hardware Mode Strapping

and PHY Addressing for details.

R/GMII

TX_CLK

I, PD

VDDMAC

RGMII transmit clock input

R/GMII

TX_EN/TX_CTL

I, PD

VDDMAC

MII transmit data enable input/RGMII

transmit data control input

R/GMII

TX_ER

I, PD

VDDMAC

MII transmit data error input

R/GMII

TXD0

I, PD

VDDMAC

RGMII/MII data input

R/GMII

TXD1

I, PD

VDDMAC

RGMII/MII data input

R/GMII

TXD2

I, PD

VDDMAC

RGMII/MII data input

R/GMII

TXD3

I, PD

VDDMAC

RGMII/MII data input

TABLE 3-2:

PINS BY FUNCTION

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