PIC16F88-ISLASHSS datasheet(32/214 Pages) MICROCHIP

32 / 214 page

PIC16F87/88

DS30487B-page 30

Preliminary

 2003 Microchip Technology Inc.

3.5

Reading FLASH Program Memory

To read a program memory location, the user must

write two bytes of the address to the EEADR and

EEADRH registers, set the EEPGD control bit

(EECON1<7>),

and

then

set

control

bit

(EECON1<0>). Once the read control bit is set, the

program memory FLASH controller will use the second

instruction cycle to read the data. This causes the

second instruction immediately following the “BSF

EECON1,RD

” instruction to be ignored. The data is

available in the very next cycle in the EEDATA and

EEDATH registers; therefore, it can be read as two

bytes in the following instructions. EEDATA and

EEDATH registers will hold this value until another read

or until it is written to by the user (during a write

operation).

EXAMPLE 3-3:

FLASH PROGRAM READ

3.6

Erasing FLASH Program Memory

The minimum erase block is 32 words. Only through

the use of an external programmer, or through ICSP

control, can larger blocks of program memory be bulk

erased. Word erase in the FLASH array is not

supported.

When initiating an erase sequence from the microcon-

troller itself, a block of 32 words of program memory is

erased.

The

Most

Significant

bits

the

EEADRH:EEADR point to the block being erased.

EEADR< 4:0> are ignored.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the FLASH pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

For protection, the write initiate sequence for EECON2

must be used.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to setup the erase operation. The

user must place two NOP instructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms, only during the cycle in which the erase

takes place. This is not SLEEP mode, as the clocks and

peripherals will continue to run. After the erase cycle,

the processor will resume operation with the third

instruction after the EECON1 write instruction.

3.6.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

Load EEADRH:EEADR with address of row

being erased.

Set EEPGD bit to point to program memory, set

WREN bit to enable writes, and set FREE bit to

enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write AAh to EECON2.

Set the WR bit. This will begin the row erase

cycle.

The CPU will stall for duration of the erase.

BANKSEL EEADRH

; Select Bank of EEADRH

MOVF

ADDRH, W

;

MOVWF

EEADRH

; MS Byte of Program

; Address to read

MOVF

ADDRL, W

;

MOVWF

EEADR

; LS Byte of Program

; Address to read

BANKSEL EECON1

; Select Bank of EECON1

BSF

EECON1, EEPGD ; Point to PROGRAM

; memory

BSF

EECON1, RD

; EE Read

;

NOP

; Any instructions

; here are ignored as

NOP

; program memory is

; read in second cycle

; after BSF EECON1,RD

BANKSEL EEDATA

; Select Bank of EEDATA

MOVF

EEDATA, W

; DATAL = EEDATA

MOVWF

DATAL

;

MOVF

EEDATH, W

; DATAH = EEDATH

MOVWF

DATAH

;

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