PIC16F88-ISLASHSS datasheet(95/214 Pages) MICROCHIP

95 / 214 page

 2003 Microchip Technology Inc.

Preliminary

DS30487B-page 93

PIC16F87/88

10.3.1.1

Addressing

Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condi-

tion, the eight bits are shifted into the SSPSR register.

All incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The buffer full bit, BF, is set.

An ACK pulse is generated.

SSP interrupt flag bit, SSPIF (PIR1<3>), is set

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave device. The five Most Significant

bits (MSbs) of the first address byte specify if this is a

10-bit address. Bit R/W (SSPSTAT<2>) must specify a

write so the slave device will receive the second

address byte. For a 10-bit address, the first byte would

equal ‘1111 0 A9 A8 0’, where A9 and A8 are the

two MSbs of the address.

The sequence of events for 10-bit address is as

follows, with steps 7- 9 for slave transmitter:

Receive first (high) byte of address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

Update the SSPADD register with the first (high)

byte of Address, if match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated START condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

10.3.1.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

a no Acknowledge (ACK) pulse is given. An overflow

condition is indicated if either bit, BF (SSPSTAT<0>), is

set or bit, SSPOV (SSPCON<6>), is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF (PIR1<3>), must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

10.3.1.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and pin RB4/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then, pin RB4/SCK/SCL should be enabled by set-

ting bit CKP (SSPCON<4>). The master device must

monitor the SCL pin prior to asserting another clock

pulse. The slave devices may be holding off the master

device by stretching the clock. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time (Figure 10-7).

An SSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF, must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit, SSPIF, is set on the falling edge of

the ninth clock pulse.

As a slave transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the data transfer is complete. When the ACK is latched

by the slave device, the slave logic is reset (resets

SSPSTAT register) and the slave device then monitors

for another occurrence of the START bit. If the SDA line

was low (ACK), the transmit data must be loaded into

the SSPBUF register, which also loads the SSPSR reg-

ister. Then, pin RB4/SCK/SCL should be enabled by

setting bit CKP.

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