PIC16F88-ISLASHSS datasheet(13/214 Pages) MICROCHIP

13 / 214 page

 2003 Microchip Technology Inc.

Preliminary

DS30487B-page 11

PIC16F87/88

2.0

MEMORY ORGANIZATION

There are two memory blocks in the PIC16F87/88

devices. These are the program memory and the data

memory. Each block has its own bus so access to each

block can occur during the same oscillator cycle.

The data memory can be further broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

The data memory area also contains the data EEPROM

memory. This memory is not directly mapped into the

data memory but is indirectly mapped. That is, an indi-

rect address pointer specifies the address of the data

EEPROM memory to read/write. The PIC16F87/88

device’s 256 bytes of data EEPROM memory have the

address range 00h-FFh. More details on the EEPROM

memory can be found in Section 3.0 “Data EEPROM

and FLASH Program Memory”.

Additional information on device memory may be found

in the PICmicro® Mid-Range Reference Manual

(DS33023).

2.1

Program Memory Organization

The PIC16F87/88 devices have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. For the PIC16F87/88, the first 4K x 14

(0000h-0FFFh)

physically

implemented

(see

Figure 2-1). Accessing a location above the physically

implemented address will cause a wraparound. For

example, the same instruction will be accessed at loca-

tions 020h, 420h, 820h, C20h, 1020h, 1420h, 1820h,

and 1C20h.

The RESET vector is at 0000h and the interrupt vector

is at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK: PIC16F87/88

2.2

Data Memory Organization

The Data Memory is partitioned into multiple banks that

contain the General Purpose Registers and the Special

Function Registers. Bits RP1 (STATUS<6>) and RP0

(STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain SFRs.

Some “high use” SFRs from one bank may be mirrored

in another bank for code reduction and quicker access

(e.g., the STATUS register is in Banks 0-3).

RP1:RP0

Bank

Note:

EEPROM data memory description can be

found in Section 3.0 “Data EEPROM and

FLASH Program Memory” of this data

sheet.

PC<12:0>

0000h

0004h

0005h

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip

CALL, RETURN

RETFIE, RETLW

1FFFh

Stack Level 2

Program

Memory

Page 0

07FFh

Wraps to

0000h - 03FFh

Page 1

0FFFh

1000h

0800h

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