PIC16F88-ISLASHSS datasheet(99/214 Pages) MICROCHIP

99 / 214 page

 2003 Microchip Technology Inc.

Preliminary

DS30487B-page 97

PIC16F87/88

11.0

ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI.) The USART can be con-

figured as a full-duplex asynchronous system that can

communicate with peripheral devices, such as CRT ter-

minals and personal computers, or it can be configured

as a half-duplex synchronous system that can commu-

nicate with peripheral devices, such as A/D or D/A

integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous - Master (half-duplex)

• Synchronous - Slave (half-duplex)

Bit SPEN (RCSTA<7>) and bits TRISB<5,2> have to

be set in order to configure pins, RB5/SS/TX/CK and

RB2/SDO/RX/DT,

the

Universal

Synchronous

Asynchronous Receiver Transmitter.

The USART module also has a multi-processor

communication

capability,

using

9-bit

address

detection.

TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)

R/W-0

U-0

R/W-0

R-1

R/W-0

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

bit 7

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

= Master mode (clock generated internally from BRG)

= Slave mode (clock from external source)

bit 6

TX9: 9-bit Transmit Enable bit

= Selects 9-bit transmission

= Selects 8-bit transmission

bit 5

TXEN: Transmit Enable bit

= Transmit enabled

= Transmit disabled

Note:

SREN/CREN overrides TXEN in Sync mode.

bit 4

SYNC: USART Mode Select bit

= Synchronous mode

= Asynchronous mode

bit 3

Unimplemented: Read as ‘0’

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

= High-speed

= Low-speed

Synchronous mode:

Unused in this mode.

bit 1

TRMT: Transmit Shift Register Status bit

= TSR empty

= TSR full

bit 0

TX9D: 9th bit of Transmit Data, can be Parity bit

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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