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L9374LF 데이터시트(PDF) 44 Page - STMicroelectronics

부품명 L9374LF
상세설명  Four channel valve driver
PDF  80 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9374LF 데이터시트(HTML) 44 Page - STMicroelectronics

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DocID025414 Rev 1
Figure 28. Thermal detection / protection behavior.
4.8.5
Power ground loss (PGND-loss)
PGND-loss continuously monitors the voltage between SGND and PGNDxy. If the
measured value is higher than VPG_L (Table 16) for longer than tPGND_L (Table 18) a failure
is detected. This sets the PGNDL_Qx bit (Section 5.2.2) and sets all of the set point and
control variables to zero disabling the output. There is a power ground loss bit for each
output even though Output 1 shares power ground with Output 2 and Output 3 shares
power ground with Output 4. It is not possible to switch on the output as long as the failure is
detected.
Once the power ground loss condition is removed the outputs are re-enabled by reading the
appropriate status register (SPI Status register 1 - 4). This clears the failure bit in the status
register and re-enables the output for use. This failure detection is used for all outputs.
The status of the failure is shown via SPI. PGND-loss is latched and can be reset only by
accessing this register when the failure does not exist anymore.
4.8.6
Signal ground loss (SGND-loss)
The SGND-loss monitors the voltage between SGND and PGNDxy. If the measured value is
higher than VSG_L (Table 16) for tSGND_L (Table 18) a failure is detected. After this time ALL
outputs are switched off immediately and the driver is shut down. The SPI communication is
possible but there is a threshold shift at the logic output drivers due to an additional
substrate diode in the ground path between PGNDxy and SGND (see Section 5.2.1).
4.8.7
Freewheeling diode loss detection (Dx-loss)
Freewheeling diode loss is detected by measuring the current through the output clamping
structure. If the clamping structure is used for more than tDX_L(Table 18) a Dx_Loss is
detected and the appropriate Status register bit (bit D5 of status registers 1 - 4,
Section 5.2.2) is latched on. This bit can only be cleared once the failure is removed and the
status register is read.



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