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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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L9961 데이터시트(PDF) 21 Page - STMicroelectronics |
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L9961 데이터시트(HTML) 21 Page - STMicroelectronics |
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21 / 63 page  NTC measurements are stored in the NTC_MEAS register and are compared to programmable thresholds in order to detect the failures listed in Table 16. Table 14. NTC temperature monitor diagnostics Fault type Assertion condition IC reaction to assertion Release condition IC reaction to flag clear Maskable NTC OT If NTC voltage falls below NTC_OT_TH, the corresponding OT counter is incremented by 1 The NTC_OT flag is set If NTC voltage raises above NTC_OT_TH, the corresponding OT counter is decremented by 1. The charge FET is restored to the status defined by the CHG_ON bit NTC_EN masks measurement execution. The OT flag of a disabled NTC can always be cleared If the OT counter reaches NTC_OT_CNT_TH, the NTC OT fault is acknowledged The charge FET is turned OFF If the OT counter reaches zero, the NTC OT flag can be cleared by MCU FAULTN line is released NTC_OT_PRDRV_MS K masks reaction on CHG pin FAULTN line is asserted NTC_OT_FAULTN_MS K masks reaction on FAULTN pin Severe NTC OT If a NTC voltage falls below NTC_SEVERE_OT_TH , the severe OT fault is acknowledged The NTC_SEVERE_OT flag is set If NTC voltage raises above NTC_SEVERE_OT_TH , the severe OT flag can be cleared by MCU The charge FET is restored to the status defined by the CHG_ON bit NTC_EN masks measurement execution. When disabled, the severe OT flag can always be cleared Both charge and discharge FETs are turned OFF The discharge FET is restored to the status defined by the DCHG_ON bit NTC_SEVERE_OT_P RDRV_MSK masks reaction on CHG/ DCHG pins Balancing is interrupted on all cells FUSE pre-driver is disabled NTC_SEVERE_OT_FU SE_MSK masks reaction on FUSE pin FUSE pre-driver is enabled Balancing FETs are restored to the status defined by the corresponding BAL<x>_ON bit NTC_SEVERE_OT_BA L_MSK masks reaction on balancing FAULTN line is asserted FAULTN line is released NTC_SEVERE_OT_FA ULTN_MSK masks reaction on FAULTN pin NTC UT If NTC voltage raises above NTC_UT_TH, the corresponding UT counter is incremented by 1 The NTC_UT flag is set If NTC voltage falls below NTC_UT_TH, the corresponding UT counter is decremented by 1. The charge FET is restored to the status defined by the corresponding I2C bit NTC_EN masks measurement execution. The UT flag of a disabled NTC can always be cleared If the UT counter reaches NTC_UT_CNT_TH, the NTC UT fault is acknowledged The Charge FET is turned OFF If the UT counter reaches zero, the NTC_UT flag can be cleared by MCU FAULTN line is released NTC_UT_PRDRV_MS K masks reaction on CHG pin FAULTN line is asserted NTC_UT_FAULTN_MS K masks reaction on FAULTN pin 3.4.3.1 Electrical parameters All parameters are tested and guaranteed in the following conditions, unless otherwise noted: VB according operating range of Table 4 ; TJ according operating range of Table 7. L9961 Voltage conversion routine DS14012 - Rev 1 page 21/63 |
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