L9961 datasheet(39/63 Pages) STMICROELECTRONICS

39 / 63 page

3.9.1

Clock polarity

Figure 11. I2C clock polarity

GADG220620221330SA

Data on SDA line is sampled upon SCL rising edge and it must fulfill tSU_DAT (setup) and tHD_DAT (hold)

constraints. While it is allowed to change during SCL low semi-period. A single bit is transferred per each clock

period.

3.9.2

START/STOP conditions

Figure 12. I2C START/STOP conditions

GADG220620221332SA

SDA

SCL

Start condition

Stop condition

Every communication window is defined within START and STOP conditions. These are always generated by the

master

•

A START condition corresponds to a SDA HI→LO transition while SCL is HIGH. The SCL must verify the

tSU_STA (setup) and tHD_STA (hold) constraints

–

When a START condition is detected an internal watchdog timer is reset and started

•

A STOP condition corresponds to a SDA LO→HI transition while SCL is HIGH. The SCL must verify the

tSU_STO (setup) and tHD_STO (hold) constraints

–

If the communication break or any issue occur while a I2C frame is ongoing, the IC will be able to

re-engage after TI2C_TIMEOUT time.

After the STOP condition, the bus must be left idle for at least tBUF before issuing a new START condition. L9961

resets its I2C logic upon each START/STOP condition detection.

L9961

I2C communication interface

DS14012 - Rev 1

page 39/63

L9961 데이터시트(PDF) 39 Page - STMicroelectronics