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L9961 데이터시트(PDF) 33 Page - STMicroelectronics |
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L9961 데이터시트(HTML) 33 Page - STMicroelectronics |
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33 / 63 page ![]() Figure 9. Balancing timing diagram GADG220620221343SA 3.6.1 Electrical parameters All parameters are tested and guaranteed in the following conditions, unless otherwise noted: VB according operating range of Table 4; TJ according operating range of Table 7. Table 24. Balancing electrical parameters Symbol Parameter Test conditions Min. Typ. Max. Unit Pin RDS_ON Balancing FET ON resistance IOUT=70 mA 20 Ω Cx IBAL_MAX Maximum balancing current For each balancing FET 70 mA Cx TON_BAL Cell balance driver turn on time RCx=39 Ω, external Cap 470 nF From BAL<x>_ON command to 30% of VDS 1 5 12 µs Cx TOFF_BAL Cell balance driver turn off time RCx=39 Ω, external Cap 470nF From BAL<x>_OFF command to 70% of VDS 3 9 20 µs Cx TBAL_SETTLING Settling time before cell measurement Tested by SCAN TMEAS_CYCLE/8 ms Cx 3.7 HS/LS pre-drivers (CHG/DCHG/FUSE) L9961 integrates three pre-driver stages aimed at managing pack connection to external loads and chargers. 3.7.1 Battery pack charge/discharge relays (CHG/DCHG) L9961 uses a dual pre-driver stage to manage the external charge (CHG) and discharge (DCHG) switches. The pre-driver stage can be configured as high side or low side by programming the CHG_HS_LS and DCHG_HS_LS field. The gate driver outputs are enabled in NORMAL mode only, and are in HiZ while in STANDBY or SHIPMENT - DEEP SLEEP states. When in NORMAL state, the CHG an DCHG FETs can be commanded ON/OFF using I2C registers: • DCHG_ON commands the DCHG FET • CHG_ON commands the CHG FE Several diagnostics may have an impact on CHG/DCHG output state, which can be forced low by L9961 independently of the status of the above commands. 3.7.1.1 Electrical parameters All parameters are tested and guaranteed in the following conditions, unless otherwise noted: VB according operating range of Table 4; TJ according operating range of Table 7. L9961 HS/LS pre-drivers (CHG/DCHG/FUSE) DS14012 - Rev 1 page 33/63 |
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