HC08KL8GRSSLASHD datasheet(49/256 Pages) NXP

49 / 256 page

MC68HC08KL8 — Rev. 2.0

General Release Specification

Random-Access Memory (RAM)

General Release Specification — MC68HC08KL8

Section 3. Random-Access Memory (RAM)

3.1 Contents

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3.2 Introduction

This section describes the 368 bytes of random-access memory (RAM).

3.3 Functional Description

Addresses $0040–$01AF are RAM locations. The location of the stack

RAM is programmable. The 16-bit stack pointer allows the stack to be

anywhere in the 64-Kbyte memory space.

NOTE:

For correct operation, the stack pointer must point only to RAM

locations.

Within page zero are 192 bytes of RAM. Because the location of the

stack RAM is programmable, all page zero RAM locations can be used

for I/O control and user data or code. When the stack pointer is moved

from its reset location at $00FF, direct addressing mode instructions can

access efficiently all page zero RAM locations. Page zero RAM,

therefore, provides ideal locations for frequently accessed global

variables.

Before processing an interrupt, the CPU uses five bytes of the stack to

save the contents of the CPU registers.

NOTE:

For M6805 Family compatibility, the H register is not stacked.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D 데이터시트(PDF) 49 Page - NXP Semiconductors