HC08KL8GRSSLASHD datasheet(98/256 Pages) NXP

98 / 256 page

System Integration Module (SIM)

General Release Specification

MC68HC08KL8 — Rev. 2.0

System Integration Module (SIM)

NOTE:

External crystal applications should use the full stop recovery time by not

selecting the SSREC option.

A break interrupt during stop mode sets the SIM break stop/wait bit

(SBSW) in the break status register (BSR).

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of stop recovery. It is then used to time the

recovery period. Figure 8-17 shows stop mode entry timing.

NOTE:

To minimize stop current, all pins configured as inputs should be driven

to a logic 1 or logic 0.

Figure 8-17. Stop Mode Entry Timing

Figure 8-18. Stop Mode Recovery from Interrupt or Break

STOP ADDR + 1

SAME

IAB

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

STOP ADDR

SAME

R/W

CPUSTOP

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

CGMXCLK

INT/BREAK

IAB

STOP + 2

SP – 1

SP – 2

SP – 3

STOP +1

STOP RECOVERY PERIOD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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