HC08KL8GRSSLASHD datasheet(101/256 Pages) NXP

101 / 256 page

System Integration Module (SIM)

SIM Registers

MC68HC08KL8 — Rev. 2.0

General Release Specification

System Integration Module (SIM)

8.8.2 Reset Status Register

This register contains six flags that show the source of the last reset. All

flag bits are cleared automatically following a read of the register. The

other bits cleared. However, during a POR or any other internal reset,

the RST pin is pulled low. After the pin is released, it will be sampled 32

CGMXCLK cycles later. If the pin is not above a VIH at that time, then the

PIN bit in the RSR may be set in addition to whatever other bits are

set.

POR — Power-On Reset Bit

1 = A POR has occurred.

0 = Read of RSR

PIN — External Reset Bit

1 = An external reset has occurred since the last read of the

RSR.

0 = Read of RSR

COP — Computer Operating Properly Reset Bit

1 = A COP reset has occurred since the last read of the

RSR.

0 = POR or read of RSR

ILOP — Illegal Opcode Reset Bit

1 = An illegal opcode reset has occurred since the last read

of the RSR.

0 = POR or read of RSR

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

USB

Write:

POR:

10000000

= Unimplemented

Figure 8-20. Reset Status Register (RSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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