P9222-R/RN Datasheet

© 2019-2022 Renesas Electronics Corporation

43

May 5, 2022

Table 13. Status Registers, Status_L (0x34), Status_H (0x35)

Address

and Bit

Register Field Name

R/W

Default

Value

Function and Description

0x34 [7]

Reserved

R

0x0

Reserved

0x34 [6]

VRECTON

R

0x0

1 = Indicates AC power is applied. The flag is set before the Configuration Packet. It

is cleared on system reset or when power is removed. Interrupt event is generated

on SET event. This bit can be used for turning on the charging indicator on the

receiver.

0x34 [5]

TX Data Received

R

0x0

0 = Indicates no TX data is received.

1 = Indicates TX data is received and is ready to be read

0x34 [4]

Over voltage

R

0x0

0 = Indicates no such a condition exists.

1 = Indicates Over Voltage condition exists

0x34 [3]

Over current

R

0x0

0 = Indicates no such a condition exists

1 = Indicates Over Current condition exists

0x34 [2]

Over temperature

R

0x0

0 = Indicates no such a condition exists

1 = Indicates Over Temperature condition exists

0x34 [1:0]

Reserved

R

0x0

Reserved

0x35 [7:0]

Reserved

R

0x0

Reserved

Table 14. Interrupt Registers, INT_L (0x36), INT_H (0x37)[a]

Address

and Bit

Register Field Name

R/W

Default

Value

Function and Description

0x36 [7]

Reserved

R

0x0

Reserved.

0x36 [6]

VRECTON_INT

R

0x0

AC power applied and stable interrupt.

0x36 [5]

TX Data Received

R

0x0

1 = Indicates a pending interrupt for TX Data Received. (No received data state

change to data received state).

0x36 [4]

Over voltage

R

0x0

1 = Indicates a pending interrupt for Over voltage event

0x36 [3]

Over current

R

0x0

1 = Indicates a pending interrupt for Over current event

0x36 [2]

Over temperature

R

0x0

1 = Indicates a pending interrupt for Over temperature event

0x36 [1]

Reserved

R

0x0

Reserved

0x36 [0]

Mode_Changed

R

0x0

1 = Indicates a pending interrupt for mode or state change. For reading the current

state, refer to Sys_Op_Mode (0x4C).

0x37 [7:0]

Reserved

R

0x00

Reserved

[a] If any bit in the two INT status registers is 1, and the corresponding bit in the two INT Enable registers is set to 1, /INT pad will be pulled down

to indicate an interrupt event to AP.