P9222-R datasheet(44/58 Pages) RENESAS

44 / 58 page

P9222-R/RN Datasheet

May 5, 2022

Table 15. Interrupt Enable Registers, INT_Enable_L (0x38), INT_Enable_H (0x39)

Address

and Bit

R/W

Default

Value

Function and Description

0x38 [6]

VRECTON_EN

R/W

0x1

AC power applied and stable interrupt enable.

0x38 [5]

TX Data Received

R/W

0x0

0 = Disable the interrupt.

1 = AP writes 1 to enable the interrupt from Interrupt Registers’ corresponding bit.

0x38 [4]

Over voltage

R/W

0x1

0 = Disable the interrupt.

1 = AP writes 1 to enable the interrupt from Interrupt Registers’ corresponding bit.

0x38 [3]

Over current

R/W

0x1

0 = Disable the interrupt.

1 = AP writes 1 to enable the interrupt from Interrupt Registers’ corresponding bit.

0x38 [2]

Over temperature

R/W

0x1

0 = Disable the interrupt.

1 = AP writes 1 to enable the interrupt from Interrupt Registers’ corresponding bit.

0x38 [1]

Reserved

0x0

Reserved

0x38 [0]

Mode Changed

R/W

0x0

0 = Disable the interrupt.

1 = AP writes 1 to enable the interrupt from Interrupt Registers’ corresponding bit.

0x39 [7:0]

Reserved

0x00

Reserved

Table 16. Interrupt Clear Registers, INT_Clear_L (0x3A), INT_Clear_H (0x3B)

Address

and Bit

R/W

Default

Value

Function and Description

0x3A [6]

VRECTON_CLR

R/W

0x0

AC power applied and stable interrupt clear.

0x3A [5]

TX Data Received

R/W

0x0

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is

self-cleared to 0 (by M0) afterward.

0x3A [4]

Over voltage

R/W

0x0

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is

self-cleared to 0 (by M0) afterward.

0x3A [3]

Over current

R/W

0x0

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is

self-cleared to 0 (by M0) afterward.

0x3A [2]

Over temperature

R/W

0x0

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is

self-cleared to 0 (by M0) afterward.

0x3A [1]

Reserved

0x0

Reserved.

0x3A [0]

Stat_Mode_Changed

R/W

0x0

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is

self-cleared to 0 (by M0) afterward.

0x3B [7:0]

Reserved

0x00

Reserved

Clearing all interrupts:

Clear all the interrupts that were generated using the INT_Clear_L (0x3A) and COM (0x4E) registers:

1. Write 0xFF to the INT_Clear_L (0x3A) register.

2. Write 0x20 to the COM (0x4E) register (set bit 5) to instruct the processor to clear the interrupt.

P9222-R 데이터시트(PDF) 44 Page - Renesas Technology Corp

P9222-R 데이터시트(HTML) 44 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

데이터시트 다운로드

링크 URL