DSP56600FMSLASHAD datasheet(37/76 Pages) NXP

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Pin and Signal Descriptions

DSP56651 Signal Description

Preliminary

MOTOROLA

DSP56651 Technical Data Sheet

1-31

Serial Audio Codec Port

After reset, the default state of all serial audio codec pins is Hi-Z. For serial audio

codec port signals equipped with resistors, all pull-ups and pull-downs are

automatically disconnected when the pin is an output.

Table 1-18

Serial Audio Codec Port Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

STDA

Input or

Output

Input

Audio codec transmit data

— This output signal transmits serial

data from the audio codec serial transmitter shift register. It is

equipped with a 100k

Ω pull-up resistor.

This is a GPIO signal when STDA is not being used.

Note:

This signal is disabled if the alternate STDA function on

INT6 is selected. (See Table 1-12 on page 1-19.)

SRDA

Input or

Output

Input

Audio codec receive data

— This input signal receives serial data

and transfers the data to the audio codec receive shift register. It is

equipped with a 100k

Ω pull-down resistor.

This is a GPIO signal when SRDA is not being used.

Note:

This signal is disabled if the alternate SRDA function on

INT7 is selected. (See Table 1-12 on page 1-19.)

SCKA

Input or

Output

Input

Audio codec serial clock

— This bidirectional signal provides the

serial bit rate clock when only one clock is being used or the TxD

clock otherwise. It is equipped with a 100k

Ω pull-down resistor.

This is a GPIO signal when the serial audio codec port is not being

used.

Note:

This signal is disabled if the alternate SCKA function on

ROW7 is selected. (See Table 1-14 on page 1-22.)

SC0A

Input or

Output

Input

Audio codec serial clock 0—

This signal’s function is determined by

the SCLK mode.

•

Synchronous mode—serial I/O flag 0

•

Asynchronous mode—receive clock I/O

This is a GPIO signal when SC0A is not being used.

SC1A

Input or

Output

Input

Audio codec serial clock 1—

This signal’s function is determined by

the SCLK mode.

•

Synchronous mode—serial I/O flag 0

•

Asynchronous mode—receiver frame sync I/O

This is a GPIO signal when SC1A is not being used.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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