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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56600FM/AD 데이터시트(PDF) 48 Page - NXP Semiconductors |
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DSP56600FM/AD 데이터시트(HTML) 48 Page - NXP Semiconductors |
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48 / 76 page  Preliminary 2-6 DSP56651 Technical Data Sheet MOTOROLA Specifications Phase-Locked Loop (PLL) Characteristics PHASE-LOCKED LOOP (PLL) CHARACTERISTICS RESET, MODE SELECT, AND INTERRUPT TIMING Table 2-8 Phase-Locked Loop (PLL) Characteristics Characteristics Expression Min Max Unit VCO frequency when PLL enabled1 MF × EfD × 2 / PDF 30 120 MHz PLL external capacitor (PCAP pin to VCCP) • MF ≤ 4 • MF > 4 CPCAP 2 (680 • MF-120) recommended (580 • MF-100) minimum (780 • MF-140) maximum (1100 • MF) recommended (830 • MF) minimum (1470 • MF) maximum pF Notes: 1. The VCO output is further divided by 2 when PLL is enabled. If the division factor (DF) is 1, the operating frequency is . 2. CPCAP is the value of the PLL capacitor (connected between PCAP pin and VCCP). (The recommended value for Cpcap is (680 × MF – 120) pF for MF ≤ 4 and (1100 × MF) pF for MF > 4.) Table 2-9 Reset, Mode Select, and Interrupt Timing Num Characteristics Expression MCU @16.8 MHz DSP @58.8 MHz Unit Min Max 1 RESET_IN duration to guarantee reset 3 × T CKIL + 0.05 91.6 — µs 2 Delay from RESET_IN assertion to RESET_OUT assertion min: 4.5 × T CKIL max: 5.5 × T CKIL 137.33 167.85 µs 3 Duration of RESET_OUT assertion 7 × T CKIL 213.62 — µs 4 Delay from RESET_IN assertion to all pins at Reset Value (periodically sampled and not 100% tested) min: 4.5 × T CKIL max: 5.5 × T CKIL 137.33 167.85 µs µs 5 MOD select setup time 3.5 × T CKIL + 0.02 107 — µs 6 MOD select hold time — 0 — ns 7 Minimum edge-triggered DSP_IRQ assertion width —10 — ns 8 Minimum edge-triggered DSP_IRQ deassertion width —10 — ns VCO 2 ------------- Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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