| 전자부품 데이터시트 검색엔진 |
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DSP56600FM/AD 데이터시트(PDF) 56 Page - NXP Semiconductors |
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DSP56600FM/AD 데이터시트(HTML) 56 Page - NXP Semiconductors |
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56 / 76 page ![]() Preliminary 2-14 DSP56651 Technical Data Sheet MOTOROLA Specifications Audio Serial Codec and Baseband Serial Codec Timing Table 2-13 SAP and BBP Timing Num Characteristics Symbol Expression DSP @ 58.8 MHz Case Unit Min Max 430 Clock cycle1 tSSICC 4 × TDC 3 × TDC 68 51 — — i ck x ck ns ns 431 Clock high period for internal clock for external clock — 2 × TDC – 12.2 1.5 × TDC 21.8 25.5 — — ick xck ns ns 432 Clock low period for internal clock for external clock — 2 × TDC – 12.2 1.5 × TDC 21.8 25.5 — — ick xck ns ns 433 RXC rising edge to FSR out (bl) high — — — — 45.1 26.8 x ck i ck a ns ns 434 RXC rising edge to FSR out (bl) low — — — — 45.1 26.8 x ck i ck a ns ns 435 RXC rising edge to FSR out (wr) high2 —— — — 47.6 29.3 x ck i ck a ns ns 436 RXC rising edge to FSR out (wr) low2 —— — — 47.6 29.3 x ck i ck a ns ns 437 RXC rising edge to FSR out (wl) high — — — — 45.9 25.6 x ck i ck a ns ns 438 RXC rising edge to FSR out (wl) low — — — — 45.1 26.8 x ck i ck a ns ns 439 Data in setup time before RXC (SCK in synchronous mode) falling edge — — 0.0 23.2 — — x ck i ck ns ns 440 Data in hold time after RXC falling edge — — 6.1 3.6 — — x ck i ck ns ns 441 FSR input (bl, wr) high before RXC falling edge2 — — 1.2 28.0 — — x ck i ck a ns ns 442 FSR input (wl) high before RXC falling edge — — 1.2 28.0 — — x ck i ck a ns ns 443 FSR input hold time after RXC falling edge — — 3.6 0.0 — — x ck i ck a ns ns 444 Flags input setup before RXC falling edge — — 0.0 23.2 — — x ck i ck s ns ns 445 Flags input hold time after RXC falling edge — — 7.3 0.0 — — x ck i ck s ns ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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