Preliminary Electrical Characteristics

Preliminary

Freescale Semiconductor

23

Figure 11. FlexBus Read Timing.

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

Notes

Frequency of Operation

—

80

Mhz

FB1

Clock Period (FB_CLK)

—

12.5

ns

FB2

Address, Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)

—7.0

ns

1

NOTES:

1

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, “DDR SDRAM AC Timing

Characteristics” for SD_CS[3:0] timing.

FB3

Address, Data, and Control Output Hold (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)

1—

ns

1, 2

2

The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference

Manual for more information.

FB4

Data Input Setup

3.5

—

ns

FB5

Data Input Hold

0—

ns

FB6

Transfer Acknowledge (TA) Input Setup

4—

ns

FB7

Transfer Acknowledge (TA) Input Hold

0—

ns

FB8

Address Output Valid (A[23:0])

—6.0

ns

3

3

These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.

FB9

Address Output Hold (A[23:0])

1—

ns

FB_CLK

A[23:0]

D[31:0]

R/W

TS

FB_CSn

OE

TA

FB1

A[23:0]

FB2

FB3

FB4

FB5

FB6

FB7

DATA

BE/BWEn