MCF5373CAB180 datasheet(34/42 Pages) FREESCALE

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MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 22. MII Receive Signal Timing Diagram

5.14.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,

FEC_TXER, FEC_TXCLK)

Table 19 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_TXCLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from

either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options

allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 19. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid

—

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

—

FEC_TXCLK pulse width high

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

35%

65%

FEC_TXCLK period

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

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