AD9549 datasheet(72/78 Pages) AD

72 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 72 of 78

Monitor

0300; Status: This register contains the status of the chip. This register is read-only and live update.

[0] Frequency Lock Detect: This flag indicates that the “Frequency Lock Detect” circuit has detected frequency lock.

[1] Phase Lock Detect: This flag indicates that the “Phase Lock Detect” circuit has detected phase lock.

[2] Free Run: DPLL is in holdover mode (free-run)

[3] Reference Selected: 0: Reference A is active. 1: Reference B is active.

[4] Frequency Estimator Done: True when the “Frequency Estimator” circuit has successfully estimated the input frequency. See

“Frequency Estimator” on Page 47.

[5] PFD Frequency too Low: This flag indicates that the Frequency Estimator failed and detected too low of a PFD frequency.

This bit is only relevant if the user is relying on the Frequency Estimator to determine the input frequency.

[6] PFD Frequency too High: This flag indicates that the Frequency Estimator failed and detected too high of a PFD frequency.

This bit is only relevant if the user is relying on the Frequency Estimator to determine the input frequency.

[7] Unused

0301; Status (continued): This register contains the status of the chip. This register is read-only and live update.

[0] RefB OOL: The “OOL” (Out of Limits) circuit has determined that Reference B is out of limits.

[1] RefB LOR: A “LOR” (Loss of Reference) has occurred on Reference B.

[2] RefB Valid: The Reference Validation circuit has successfully determined that Reference B is valid.

[3] Unused

[4] RefA OOL: The “OOL” (Out of Limits) circuit has determined that Reference A is out of limits.

[5] RefA LOR: A “LOR” (Loss of Reference) has occurred on Reference A.

[6] RefA Valid: The Reference Validation circuit has successfully determined that Reference A is valid.

[7] Unused

0302 – 0303; IRQ Status; These registers contain the chip status (Registers 0300 – 0301) at the time of IRQ.

These bits are cleared with an IRQ reset (see Register 0012, Bit 5).

0304; IRQ Mask

[0] Enter Free Run: Trigger IRQ when DPLL enters free-running (holdover) mode.

[1] Leave Free Run: Trigger IRQ when DPLL leaves free-running (holdover) mode

[2] Reference Changed: Trigger IRQ when active reference clock selection changes

[7:3] Unused

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